1. Field of the Invention
The present invention relates to a semiconductor device with lattice-mismatched zone and fabrication method thereof, and more specifically to a strained-channel transistor structure and fabrication method thereof.
2. Description of the Related Art
Size reduction of the metal-oxide-semiconductor field-effect transistor (MOSFET), including reduction of gate length and gate oxide thickness, has enabled a continuous improvement in speed performance, density, and cost per unit function of integrated circuits during the past few decades.
In order to further enhance performance of the transistor, strain may be introduced in the transistor channel to improve carrier mobility to enhance performance of the transistor in addition to device scaling. There are several existing approaches to introducing strain in a channel region of the transistor.
In one conventional approach, as described in a paper titled “NMOS and PMOS transistors fabricated in strained silicon/relaxed silicon-germanium structures”, disclosed by J. Welser et al., published at the December 1992 International Electron Devices Meeting held in San Francisco, Calif., pp. 1000-1002, a relaxed silicon germanium (SiGe) buffer layer 110 is provided beneath channel region 126, as shown in FIG. 1A. In FIG. 1B and FIG. 1C, a simple model of different lattice constants is used to show the intersection between relaxed SiGe layer 114 of buffer layer 110 and strained-Si layer 130. In FIG. 1B, model 135 shows the natural lattice constant of Si, smaller than that of SiGe shown by model 115. In FIG. 1C, when a thin layer of epitaxial Si (model 135) is grown on relaxed SiGe layer 114 (model 115), unit cell 136 of Si shown in model 135 is stretched laterally so as to be under a biaxial tensile strain. The thin layer of epitaxial Si becomes strain-Si layer 130 shown in FIG. 1A. In. FIG. 1A, a transistor formed on the epitaxial strained-Si layer 130 is therefore with a channel region 126 under the biaxial tensile strain. In this approach, relaxed SiGe layer 114 is a stressor that introduces strain in channel region 126. The stressor, in this case, is placed below channel region 126. Significant mobility enhancement has been reported for both electrons and holes in bulk transistors using a silicon channel under biaxial tensile strain. In the aforementioned approach, the epitaxial silicon layer 130 is strained before forming the transistor. Therefore, there are some concerns about possible strain relaxation in the subsequent high temperature CMOS, processes. Further, the approach is very expensive since SiGe buffer layer 110 with thickness in the order of micrometers has to be grown. Numerous dislocations exist in relaxed SiGe layer 114, some of which propagate to strained-Si layer 130, resulting in high defect density, thereby negatively affecting transistor performance.
In another approach, strain in a channel region is introduced after a transistor is formed. In this approach, a high stress film 220 is formed over a completed transistor structure 250, as shown in FIG. 2. High stress film 220, being a stressor, exerts significant influence on channel region 206, modifying silicon lattice spacing in channel region 206, and thus introducing strain in channel region 206. In this case, the stressor is placed above completed transistor structure 250, described in detail in a paper disclosed by A. Shimizu et al., entitled “Local mechanical stress control (LMC): a new technique for CMOS performance enhancement”, published in pp. 433-436 of the Digest of Technical Papers of the 2001 International Electron Device Meeting. The strain contributed by high stress film 220 is believed to be uniaxial in nature with a direction parallel to a source-to-drain direction However, uniaxial tensile strain in the source-to-drain degrades hole mobility while uniaxial compressive strain degrades electron mobility. Ion implantation of germanium can be used to selectively relax the strain so that the hole or electron mobility is not degraded, but can be difficult to implement due to the close proximity of the N and P-channel transistors.